VLSI lab - PoliTO
VLSI lab @ Dipartimento di Elettronica e Telecomunicazioni (DET) in Politecnico di Torino
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Mage-and-Rogue
Mage-and-Rogue PublicTemplate-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
Python 8
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- HORCRUX Public
vlsi-lab/HORCRUX’s past year of commit activity - cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
vlsi-lab/cva6’s past year of commit activity - x-heep Public Forked from x-heep/x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
vlsi-lab/x-heep’s past year of commit activity - VLSPQC Public
vlsi-lab/VLSPQC’s past year of commit activity - OpenSoC4HE Public
vlsi-lab/OpenSoC4HE’s past year of commit activity - riscv-Xilinx-SoCs-toolchain Public
RISC-V GCC Toolchain for X-HEEP (OpenHW Core-V) pre-build for ARM Hosts
vlsi-lab/riscv-Xilinx-SoCs-toolchain’s past year of commit activity - keccak Public
vlsi-lab/keccak’s past year of commit activity - KRONOS Public
vlsi-lab/KRONOS’s past year of commit activity
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