QLI2.0 | Shikra SoC boot enablement: LLCC, EDAC, and TLMM GPIO reserved ranges#733
QLI2.0 | Shikra SoC boot enablement: LLCC, EDAC, and TLMM GPIO reserved ranges#733apateriy-qcom wants to merge 3 commits into
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Add Last Level Cache table and configs for the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
On Shikra irq configuration is already done in firmware (in DSF or 'DDR System Firmware'). Change-Id: Idedb3ba1435cd54df8dd32c0882203b8b7e963d7 Signed-off-by: Faiyaz Mohammed <faiyazm@qti.qualcomm.com>
Add gpio-reserved-ranges property to the tlmm node for all three Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the SoC internally and not available for general use. Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com>
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
PR #733 — validate-patchPR: #733
Final Summary
Recommendation: Remove Change-Id from patch 2/3 before merge. Clarify whether these are vendor-only patches (add QCLINUX: prefix) or if upstream submission is planned (add Link: tags when available).
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PR #733 — checker-log-analyzerPR: #733
Detailed report: Full report
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Summary
This series adds boot-related enablement for the Shikra SoC on the 6.18.y branch, covering Last Level Cache (LLCC)
configuration, optional EDAC IRQ setup, and TLMM GPIO reservations across the Shikra EVK variants.
Commits
Adds the Last Level Cache table and configs for the Shikra SoC.
On Shikra, IRQ configuration is already handled in firmware (DSF / DDR System Firmware), so the driver's IRQ setup is made
optional to avoid conflicting/duplicate configuration.
Adds the gpio-reserved-ranges property to the tlmm node for all three Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs.