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frontend: Fix reg next_id launch deadlock #153

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frontend: Fix reg next_id launch deadlock #153

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c137f97
frontend: Fix reg next_id launch deadlock via pending latch
DanielKellerM Jul 8, 2026
13ba549
test: Add self-checking reg-frontend testbench with deadlock watchdog
DanielKellerM Jul 8, 2026
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1 change: 1 addition & 0 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,7 @@ sources:
# Level 1
- test/frontend/tb_idma_desc64_top.sv
- test/frontend/tb_idma_desc64_bench.sv
- test/tb_idma_reg_frontend.sv
- test/future/idma_tb_per2axi.sv
- test/future/TLToAXI4.v
- test/midend/tb_idma_nd_midend.sv
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8 changes: 8 additions & 0 deletions idma.mk
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Expand Up @@ -386,6 +386,14 @@ idma_sim_tb_idma_nd_midend_b2b: $(IDMA_VSIM_DIR)/compile.tcl
cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"
cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc tb_idma_nd_midend_b2b -do "run -all; quit"

# Self-checking reg-frontend regression (NumStreams 1 and 2); Test 2 gates the
# next_id launch deadlock. Run with the Questa SEPP wrapper.
.PHONY: idma_sim_tb_idma_reg_frontend
idma_sim_tb_idma_reg_frontend: $(IDMA_VSIM_DIR)/compile.tcl
cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"
cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gNumStreams=1 tb_idma_reg_frontend -do "run -all; quit"
cd $(IDMA_VSIM_DIR); $(VSIM) -c -t 1ps -voptargs=+acc -gNumStreams=2 tb_idma_reg_frontend -do "run -all; quit"

.PHONY: idma_sim_tb_idma_transpose_b2b
idma_sim_tb_idma_transpose_b2b: $(IDMA_VSIM_DIR)/compile.tcl
cd $(IDMA_VSIM_DIR); $(VSIM) -c -do "source compile.tcl; quit"
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29 changes: 22 additions & 7 deletions src/frontend/reg/tpl/idma_reg.sv.tpl
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Expand Up @@ -99,11 +99,15 @@ module idma_${identifier} #(
logic [NumRegs-1:0] arb_valid;
logic [NumRegs-1:0] arb_ready;

// hold the next_id launch across the read-stall (req is masked mid-stall)
logic [NumRegs-1:0][NumStreams-1:0] nxt_read_seen;
logic [NumRegs-1:0][NumStreams-1:0] nxt_read_pending_q;
Comment on lines +103 to +104

@DanielKellerM DanielKellerM Jul 8, 2026

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explain why we need extra signals.


always_comb begin
stream_idx_o = '0;
for (int r = 0; r < NumRegs; r++) begin
for (int c = 0; c < NumStreams; c++) begin
if (dma_reg2hw[r].next_id[c].req && !dma_reg2hw[r].next_id[c].req_is_wr) begin
if (nxt_read_seen[r][c] || nxt_read_pending_q[r][c]) begin
stream_idx_o = c;
end
end
Expand Down Expand Up @@ -175,14 +179,26 @@ module idma_${identifier} #(
.hwif_in ( dma_hw2reg [i] )
);

logic read_happens;
// launch-stall: hold the reg read-ack until the arbiter accepts the request
// (protocol-agnostic — driven into hwif rd_ack below, see gen_hw2reg_connections)
// next_id launch-pending latch: set on read, cleared on grant
for (genvar c = 0; c < NumStreams; c++) begin : gen_nxt_read_pending
assign nxt_read_seen[i][c] = dma_reg2hw[i].next_id[c].req
& ~dma_reg2hw[i].next_id[c].req_is_wr;
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_nxt_read_pending
if (!rst_ni) begin
nxt_read_pending_q[i][c] <= 1'b0;
end else if (nxt_read_pending_q[i][c] & arb_ready[i]) begin
nxt_read_pending_q[i][c] <= 1'b0;
end else if (nxt_read_seen[i][c] & ~arb_ready[i]) begin
nxt_read_pending_q[i][c] <= 1'b1;
end
end
end

logic read_happens;
always_comb begin : proc_launch
read_happens = 1'b0;
for (int c = 0; c < NumStreams; c++) begin
read_happens |= dma_reg2hw[i].next_id[c].req & ~dma_reg2hw[i].next_id[c].req_is_wr;
read_happens |= nxt_read_seen[i][c] | nxt_read_pending_q[i][c];
end
arb_valid[i] = read_happens;
end
Expand Down Expand Up @@ -261,8 +277,7 @@ module idma_${identifier} #(
assign dma_hw2reg[i].status[c].rd_ack = dma_reg2hw[i].status[c].req
& ~dma_reg2hw[i].status[c].req_is_wr;
assign dma_hw2reg[i].next_id[c].rd_data.next_id = next_id_i;
assign dma_hw2reg[i].next_id[c].rd_ack = dma_reg2hw[i].next_id[c].req
& ~dma_reg2hw[i].next_id[c].req_is_wr
assign dma_hw2reg[i].next_id[c].rd_ack = (nxt_read_seen[i][c] | nxt_read_pending_q[i][c])
& arb_ready[i];
assign dma_hw2reg[i].done_id[c].rd_data.done_id = done_id_i[c];
assign dma_hw2reg[i].done_id[c].rd_ack = dma_reg2hw[i].done_id[c].req
Expand Down
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