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Three quarks for Muster Mark!
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Three quarks for Muster Mark!
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albertc9/README.md

Hi, I'm Albert

Welcome to my personal website albertcheung.net

I develop hardware architectures for high-energy physics instrumentation, with a focus on FPGA prototyping. Currently, I'm developing a real-time full-band AI trigger for radio-based HE $\nu$ detectors. At the same time, we are upgrading the HERIS-V2 project, a radiation-hardened RISC-V processor designed for readout or front-end processing in HEP.





Recent News


CEPC Technical Design Report -- Reference Detector
Albert L. ZHANG, et al.








"Do not store up for yourselves treasures on earth… But store up for yourselves treasures in heaven."

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  1. Ibex Ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1

  2. NuDAQ/Hi-Lo-Trigger NuDAQ/Hi-Lo-Trigger Public

    A Hi-Lo Pre-Trigger for ARIANNA, a neutrino experiment. This module is a 4-channel trigger designed to identify coincident signal events across a 32-sample window. It utilizes a bipolar thresholdin…

    VHDL 1

  3. NuDAQ/Hi-Lo-Gated-CNN-Trigger NuDAQ/Hi-Lo-Gated-CNN-Trigger Public

    A Hi-Lo Gated CNN Trigger for ARIANNA, a neutrino experiment. This is a key submodule for the DAQ System. This module is a 4-channel trigger, composed of a Hi-Lo pre-trigger followed by an AI trigg…

    Python 1

  4. NuDAQ/pico4NuDAQ NuDAQ/pico4NuDAQ Public

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog

  5. NuDAQ/CNN-Core-Generator NuDAQ/CNN-Core-Generator Public

    A CNN Core Generator. ['cnn-core' in Bender.]

    VHDL

  6. Lilith Lilith Public

    Lilith: English Practicing Workflow

    Shell 49