Pinned Loading

1. 3-Stage-RV32IM-RISC-V-CPU 3-Stage-RV32IM-RISC-V-CPU Public

   tiny risc v implementation

   Verilog 3

2. 3-stage-riscv-golden-generator 3-stage-riscv-golden-generator Public

   ACT4/Sail golden generator for 3-stage RV32IM compliance tests

   Python

3. All-Digital-Phase-Locked-Loop-ADPLL All-Digital-Phase-Locked-Loop-ADPLL Public

   All Digital Phase-Locked Loop (ADPLL)

   Verilog

4. IEEE-Standard-754-Floating-Point-Numbers-Multiplier IEEE-Standard-754-Floating-Point-Numbers-Multiplier Public

   This project implements a 64-bit IEEE 754 double-precision floating-point multiplier using Verilog HDL.

   Verilog