diff --git a/Innopolis University/fpga_calculator_with_uart/.pictures/Terminal.png b/Innopolis University/fpga_calculator_with_uart/.pictures/Terminal.png new file mode 100644 index 0000000..81ff637 Binary files /dev/null and b/Innopolis University/fpga_calculator_with_uart/.pictures/Terminal.png differ diff --git a/Innopolis University/fpga_calculator_with_uart/.pictures/windows_COM.png b/Innopolis University/fpga_calculator_with_uart/.pictures/windows_COM.png new file mode 100644 index 0000000..324ed82 Binary files /dev/null and b/Innopolis University/fpga_calculator_with_uart/.pictures/windows_COM.png differ diff --git a/Innopolis University/fpga_calculator_with_uart/README.md b/Innopolis University/fpga_calculator_with_uart/README.md index 23f9d80..cfc55e9 100644 --- a/Innopolis University/fpga_calculator_with_uart/README.md +++ b/Innopolis University/fpga_calculator_with_uart/README.md @@ -28,14 +28,60 @@ ``` text Boundrate: 9600 Data bits: 8 + Stop bits: 2 + Parity: none ``` *Остальные по умалчанию* 4. Выбрать нужное устройство (**Device**) -5. В поле **Input** выбрать **CR** (После отправки идёт бит с возвратом каретки). + +5. В поле **Input** выбрать **CR** (После отправки идёт бит с возвратом каретки). + 6. В самом низу окна установить флаг **Hex output** + 7. Нажать на кнопку **Open** для открытия канала связи. ![CuteCome](.pictures/CuteCome.png) + +--- + +# Инструкция UART для Windows + +1. Скачать и запустить программу **Terminal**: + + `https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/terminal_win.Terminal1_9_b.zip` + + >[ссылка](https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8 "Terminal") + +2. Подключить кабель в USB разъем пк/ноутбука и посмотреть в диспетчере устройств определился ли виртуальный ComPort подлюченного преобразователя. + + ![windows_COM](.pictures/windows_COM.png) + + Если же ОС не определила его, то необходимо установить драйвер для микросхемы CH340 из: + + `https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/usb_uart_driver.ch340.zip` + + >[ссылка](https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/ "CH340") + + После чего, виртуальный ComPort должен определиться в ОС. + +3. Запускаем Terminal, устанавливаем в нём номер COM (в нашем случае 9) и другиие настройки: + + ``` text + Boundrate: 9600 + Data bits: 8 + Parity: none + Stop bits: 2 + Send: +CR + ``` + + *Остальные по умалчанию* + +4. Установить флаг **Hex** для приёма. + +5. Нажать на кнопку **Connect** для открытия канала связи. + +![Terminal](.pictures/Terminal.png) + --- diff --git a/Innopolis University/fpga_calculator_with_uart/common/data_aggregator.sv b/Innopolis University/fpga_calculator_with_uart/common/data_aggregator.sv new file mode 100644 index 0000000..3e8c25b --- /dev/null +++ b/Innopolis University/fpga_calculator_with_uart/common/data_aggregator.sv @@ -0,0 +1,28 @@ +module data_aggregator ( + input clock, + input reset, + input enter, + input add, + input multiply, + input separator, + input [3:0] data, + + output reg [7:0] number, + output reg enter_occured +); + + always @(posedge clock) begin + if (reset) begin + number <= 8'b0; + enter_occured <= 1'b0; + end else if (enter) begin + number <= {number[3:0], data}; + enter_occured <= 1'b1; + end else if (add || multiply) begin + enter_occured <= 1'b0; + end else if (separator) begin + number <= 8'b0; + end + end + +endmodule diff --git a/Innopolis University/fpga_calculator_with_uart/common/mfp_uart_receiver.sv b/Innopolis University/fpga_calculator_with_uart/common/mfp_uart_receiver.sv deleted file mode 100644 index 49614f5..0000000 --- a/Innopolis University/fpga_calculator_with_uart/common/mfp_uart_receiver.sv +++ /dev/null @@ -1,103 +0,0 @@ - -module mfp_uart_receiver ( - input clock, - input reset_n, - input rx, - - output reg [7:0] byte_data, - output byte_ready -); - parameter clock_frequency = 50000000; - parameter baud_rate = 9600; - parameter clock_cycles_in_symbol = clock_frequency / baud_rate; - - // Synchronize rx input to clock - - reg rx_sync1, rx_sync; - - always @(posedge clock or negedge reset_n) begin - if (!reset_n) begin - rx_sync1 <= 1'b1; - rx_sync <= 1'b1; - end else begin - rx_sync1 <= rx; - rx_sync <= rx_sync1; - end - end - - // Finding edge for start bit - - reg prev_rx_sync; - - always @(posedge clock or negedge reset_n) begin - if (!reset_n) prev_rx_sync <= 1'b1; - else prev_rx_sync <= rx_sync; - end - - wire start_bit_edge = prev_rx_sync & !rx_sync; - - // Counter to measure distance between symbols - - reg [31:0] counter; - reg load_counter; - reg [31:0] load_counter_value; - - always @(posedge clock or negedge reset_n) begin - if (!reset_n) counter <= 32'b0; - else if (load_counter) counter <= load_counter_value; - else if (counter != 0) counter <= counter - 1; - end - - wire counter_done = counter == 1; - - // Shift register to accumulate data - - reg shift; - reg [7:0] shifted_1; - assign byte_ready = shifted_1[0]; - - always @(posedge clock or negedge reset_n) begin - if (!reset_n) begin - shifted_1 <= 8'b0; - end else if (shift) begin - if (shifted_1 == 0) shifted_1 <= 8'b10000000; - else shifted_1 <= shifted_1 >> 1; - - byte_data <= {rx, byte_data[7:1]}; - end else if (byte_ready) begin - shifted_1 <= 8'b0; - end - end - - reg idle, idle_r; - - always @* begin - idle = idle_r; - shift = 1'b0; - - load_counter = 32'b0; - load_counter_value = 32'b0; - - if (idle) begin - if (start_bit_edge) begin - load_counter = 1; - load_counter_value = clock_cycles_in_symbol * 3 / 2; - - idle = 1'b0; - end - end else if (counter_done) begin - shift = 1'b1; - - load_counter = 1; - load_counter_value = clock_cycles_in_symbol; - end else if (byte_ready) begin - idle = 1'b1; - end - end - - always @(posedge clock or negedge reset_n) begin - if (!reset_n) idle_r <= 1'b1; - else idle_r <= idle; - end - -endmodule diff --git a/Innopolis University/fpga_calculator_with_uart/common/top.sv b/Innopolis University/fpga_calculator_with_uart/common/top.sv index a542804..e71450b 100644 --- a/Innopolis University/fpga_calculator_with_uart/common/top.sv +++ b/Innopolis University/fpga_calculator_with_uart/common/top.sv @@ -13,9 +13,9 @@ module top ( wire [7:0] ascii_data; uart_receiver listener ( - .clock (clock), - .reset_n (reset_n), - .rx (rx), + .clock (clock), + .reset_n(reset_n), + .rx (rx), .byte_data (ascii_data), .byte_ready(byte_ready) @@ -31,48 +31,48 @@ module top ( .data (ascii_data), .separator(separator), - .add (add), + .add (add), .multiply (multiply), - .digit(digit), - .enter(enter), - .clear(clear), - .error(error_ascii) + .digit (digit), + .enter (enter), + .clear (clear), + .error (error_ascii) ); // Prepare and accumulate data - reg [7:0] number; - reg enter_occured; - - always @(posedge clock) begin - if (!reset_n) begin - number <= 8'b0; - enter_occured <= 1'b0; - end else if (enter) begin - number <= {number[3:0], digit}; - enter_occured <= 1'b1; - end else if (add || multiply || error_ascii) begin - enter_occured <= 1'b0; - end else if (separator) begin - number <= 8'b0; - end - end + logic [7:0] number; + logic enter_occured; + + data_aggregator aggregator ( + .clock (clock), + .reset (~reset_n), + .enter (enter), + .add (add), + .multiply (multiply), + .separator(separator), + .data (digit), + + .number (number), + .enter_occured(enter_occured) + ); + + // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ wire [15:0] result; wire overflow, newresult; wire [3:0] error_calculator; wire is_tx_busy; - // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ calculator calculator ( - .clock(clock), - .reset(~reset_n || clear), - .enter(separator & enter_occured), - .add (add), + .clock (clock), + .reset (~reset_n || clear), + .enter (separator & enter_occured), + .add (add), .multiply(multiply), - .data (number), - + .data (number), + .newresult(newresult), .result (result), .overflow (overflow), @@ -84,17 +84,17 @@ module top ( .reset (~reset_n), .number(result), - .digit(nx_digit), + .digit (nx_digit), .abcdefgh(abcdefgh) ); - two_bytes_uart_tx loader ( + uart_transmitter loader ( .clock(clock), .reset(~reset_n), .start(newresult), .data (result), - .q(tx), + .q (tx), .busy(is_tx_busy) ); diff --git a/Innopolis University/fpga_calculator_with_uart/common/uart_tx.sv b/Innopolis University/fpga_calculator_with_uart/common/uart_transmitter.sv similarity index 86% rename from Innopolis University/fpga_calculator_with_uart/common/uart_tx.sv rename to Innopolis University/fpga_calculator_with_uart/common/uart_transmitter.sv index d2c1183..c645c94 100644 --- a/Innopolis University/fpga_calculator_with_uart/common/uart_tx.sv +++ b/Innopolis University/fpga_calculator_with_uart/common/uart_transmitter.sv @@ -1,4 +1,4 @@ -module two_bytes_uart_tx ( +module uart_transmitter ( input clock, input start, input reset, @@ -8,10 +8,14 @@ module two_bytes_uart_tx ( output busy ); + parameter clock_frequency = 50000000; + parameter baud_rate = 9600; + parameter clock_cycles_in_bit = clock_frequency / baud_rate; + reg [12:0] cnt; reg [3:0] bit_num; - wire bit_start = (cnt == 5208); + wire bit_start = (cnt == clock_cycles_in_bit); wire idle = (bit_num == 4'hF); assign busy = ~idle; @@ -27,7 +31,7 @@ module two_bytes_uart_tx ( always @(posedge clock) begin if (reset) begin - bit_num <= 4'hf; + bit_num <= 4'hF; byte_state <= 1'b0; q <= 1'b1; end else if (start && idle) begin diff --git a/Innopolis University/fpga_calculator_with_uart/de10_lite/top.qsf b/Innopolis University/fpga_calculator_with_uart/de10_lite/top.qsf index 5f792e0..8b7b1d4 100644 --- a/Innopolis University/fpga_calculator_with_uart/de10_lite/top.qsf +++ b/Innopolis University/fpga_calculator_with_uart/de10_lite/top.qsf @@ -65,10 +65,10 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv set_global_assignment -name VERILOG_FILE top.v set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tx diff --git a/Innopolis University/fpga_calculator_with_uart/omdazz/top.qsf b/Innopolis University/fpga_calculator_with_uart/omdazz/top.qsf index b3b67a0..110b10f 100644 --- a/Innopolis University/fpga_calculator_with_uart/omdazz/top.qsf +++ b/Innopolis University/fpga_calculator_with_uart/omdazz/top.qsf @@ -90,8 +90,9 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Innopolis University/fpga_calculator_with_uart/piswords/top.qsf b/Innopolis University/fpga_calculator_with_uart/piswords/top.qsf index 895b906..e5ddffd 100644 --- a/Innopolis University/fpga_calculator_with_uart/piswords/top.qsf +++ b/Innopolis University/fpga_calculator_with_uart/piswords/top.qsf @@ -73,10 +73,10 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nx_digit[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to abcdefgh[0] diff --git a/Innopolis University/fpga_calculator_with_uart/rzrd/top.qsf b/Innopolis University/fpga_calculator_with_uart/rzrd/top.qsf index 12fef85..110b10f 100644 --- a/Innopolis University/fpga_calculator_with_uart/rzrd/top.qsf +++ b/Innopolis University/fpga_calculator_with_uart/rzrd/top.qsf @@ -90,9 +90,9 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Innopolis University/fpga_calculator_with_uart/terminal_win/Terminal1_9_b.zip b/Innopolis University/fpga_calculator_with_uart/terminal_win/Terminal1_9_b.zip new file mode 100644 index 0000000..6963262 Binary files /dev/null and b/Innopolis University/fpga_calculator_with_uart/terminal_win/Terminal1_9_b.zip differ diff --git a/Innopolis University/fpga_calculator_with_uart/usb_uart_driver/ch340.zip b/Innopolis University/fpga_calculator_with_uart/usb_uart_driver/ch340.zip new file mode 100644 index 0000000..6014e5f Binary files /dev/null and b/Innopolis University/fpga_calculator_with_uart/usb_uart_driver/ch340.zip differ diff --git a/Innopolis University/fpga_calculator_with_uart/zeowaa/top.qsf b/Innopolis University/fpga_calculator_with_uart/zeowaa/top.qsf index e6f7089..3f5aee1 100644 --- a/Innopolis University/fpga_calculator_with_uart/zeowaa/top.qsf +++ b/Innopolis University/fpga_calculator_with_uart/zeowaa/top.qsf @@ -66,17 +66,16 @@ set_location_assignment PIN_132 -to nx_digit[2] set_location_assignment PIN_129 -to nx_digit[1] set_location_assignment PIN_23 -to clock - set_global_assignment -name VERILOG_INCLUDE_FILE ../common/Calculator/defines.vh set_global_assignment -name VERILOG_FILE ../common/Calculator/stack.v set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top